Binary Translation Processors

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  • Transmeta's first processor the Crusoe (see their white paper) implements the pentium architecture on a VLIW processor. They have a few hardware assists, and the current processor achieves a very low power requirement.

  • Elbrus appears to be a Russian attempt at a Transmeta type chip, i.e. implementing an X86 chip on a VLIW processor, using binary translation.

  • IBM's DAISY is a dynamic binary translator of PowerPC to VLIW code. The translator uses a fast technique to parallelise ordinary code (PowerPC or other architectures), and is being made available for download under an open source license.

  • IBM's experimental Binary-translation Optimized Architecture (BOA) aims at producing a very high frequency VLIW processor (or processors on one chip). Like Transmeta, the underlying processor is not visible to the programmer, in user or supervisor mode, and may change over time. See the IEEE "Computer" article Dynamic and Transparent Binary Translation.

  • Sun's MAJC processor (Microprocessor Architecture for Java Computing) was supposed to be an ideal target for JavaDynamicCompilers. It seems to have been cancelled.

  • Hardware assistance
    • Nazomi's JSTAR technology is a coprocessor, designed to work with any standard microprocessor, that provides a sort of hardware JIT compiler. The JSTAR coprocessor would be integrated onto the microprocessor chip, and consumes no power when not executing Java programs. When running, the coprocessor feeds native instructions into the host processor, which can be anything from 8 to 64 bits, any endianness, etc. Handles any VM as well, since the microcode can be in RAM. The JVM has to be modified to be "JSTAR aware". Performance increases of about 10x are claimed, with 30x less power when running Java applications.

-- MikeVanEmmerik - 13 Dec 2001